1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having one conductivity type impurity regions, that are formed in vicinity of two opposite conductivity type impurity diffusion regions constituting the source/drain in one conductivity type substrate respectively by the pocket injection technology, and a method of manufacturing the same.
2. Description of the Prior Art
The MOS transistor is designed based on the scaling theory. If the MOS transistor whose gate length is less than 50 nm is fabricated based on this theory, the short channel effect is generated. In order to suppress such short channel effect, for instance, the technology of increasing the n-type impurity concentration in vicinity of top ends of the n-type impurity diffusion regions serving as the source/drain in the p-type silicon substrate rather than the p-type impurity concentration of the channel region, i.e., the pocket injection technology, is being watched with interest.
Then, the application of the pocket injection technology to the steps of forming the MOS transistor will be explained hereunder.
First, as shown in FIG. 1A, the gate electrode 103 is formed on the p-type silicon substrate 101 via the gate insulating film 102. This gate electrode 103 has such a structure that the notch (pitch) 103a is formed at its lower portion, and is called the notch-type gate electrode. In FIG. 1A, a reference 106 denotes the device isolation STI (shallow trench isolation) formed in the silicon substrate 101.
Then, as shown in FIG. 1B, the p-type impurity is ion-implanted into the silicon substrate 101 in the oblique direction to the substrate surface. Thus, the p-type pocket regions 101a whose p-type impurity concentration is higher than the channel region are formed on both sides of the gate electrode 103 in the p-type silicon substrate 101. A distance between end portions of two p-type pocket regions 101a is shorter than a width (gate length) of the gate electrode 103 at the lower portion of the gate electrode 103, and also the p-type pocket regions 101a are formed away from the surface of the silicon substrate 101.
Then, as shown in FIG. 1C, the n-type impurity regions (extension regions) 104a are formed on both sides of the gate electrode 103 by ion-implanting the n-type impurity in the direction substantially perpendicular to the p-type silicon substrate 101 while using the gate electrode 103 as a mask.
Then, as shown in FIG. 1D, the insulating film is formed on the silicon substrate 101 and the gate electrode 103 by the CVD method. Then, the sidewall spacers 105 are left on the side surfaces of the gate electrode 103 by isotropic-etching the insulating film in the vertical direction. Then, the n-type impurity regions 104b of high concentration are formed on both sides of the gate electrode 103 by ion-implanting the n-type impurity into the silicon substrate 101 while using the gate electrode 103 and the sidewall spacers 105 as a mask.
The n-type impurity diffusion regions 104 serving as the source/drain and having the LDD structure are constructed by the n-type impurity diffusion regions 104a, 104b, that are formed by executing twice the ion implantation as described above, respectively. The p-type pocket regions 101a are jointed to lower portions of the end portions of the n-type impurity diffusion regions 104.
Accordingly, the channel region that is formed in vicinity of the gate electrode 103 and the p-type pocket regions 111a whose p-type impurity concentration is higher than the channel region are present between two n-type impurity diffusion regions 104.
With the above, the n-type MOS transistor is formed on the silicon layer 101. In this case, if the p-type MOS transistor is to be formed, the silicon substrate is set to the n-type, and the impurity that is ion-implanted to form the pocket regions is set to the n-type, and the impurity that is ion-implanted to form the source/drain is set to the p-type.
After such MOS transistor is formed, although not shown, the silicide layer is formed on the silicon substrate 101 and the gate electrode 103, then the interlayer insulating film for covering the MOS transistor is formed on the silicon substrate 101, and then the multi-layered wiring structure, etc. are formed on the interlayer insulating film. But their details are omitted.
The pocket injection technology that employs the notch-type gate electrode as described above is set forth in S. Piddin et.al, Symp. VLSI tec. 2001 p. 35, for example.
Meanwhile, it will be explained hereunder which pocket is formed if the pocket is formed by using the normal gate electrode having no notch portion 103a. 
First, as shown in FIG. 2A, in the situation that the gate electrode 111 whose cross section is formed as a rectangle is formed on the silicon substrate 101 via the gate insulating film 102, the p-type impurity having the same conductivity type as the silicon substrate 101 is ion-implanted (I.I) in the oblique direction to the substrate surface. In this case, since the distribution of the thickness of the gate electrode 111 is generated along the ion implantation direction of the p-type impurity, the corners of the lower portions of the gate electrode 111 are mostly reduced in thickness.
Therefore, as shown in FIG. 2B, the p-type impurity that is obliquely ion-implanted into the surface of the silicon substrate 101 exists at an almost uniform depth in the portion, in which the gate electrode 111 is not formed, out of the silicon substrate 101. However, the energy of the p-type impurity that has passed through the corners of the lower portions of the gate electrode 111 is attenuated, and thus shallow peaks are present in the silicon substrate 101. Also, the impurity that is ion-implanted via the thick portions of the gate electrode 111 is absorbed in the gate electrode 111 and does not come up to the inside of the silicon substrate 101. Accordingly, the p-type impurity high concentration region 101a has the distribution of the concentration peak such that, as shown in FIG. 2B, the concentration peak is shallow under the gate electrode 111 but is deep on both sides of the gate electrode 111.
The high concentration profile of the p-type impurity when the p-type impurity is ion-implanted into the n-type substrate 101, on which the gate electrode 111 without the notch is formed, in the oblique direction from the normal is shown in FIG. 3. In FIG. 3, as illustrated in the area encircled by a broken line, the regions in which the p-type impurity concentration is higher than the original concentration are present in the channel region in vicinity of the surface of the silicon substrate 101. In this case, the black portions in FIG. 3 denote the portion whose p-type impurity concentration is higher than the channel region.
In this manner, if the pocket portions 101a have the concentration distribution close to the channel region under the gate electrode 111, such distribution interferes with the increase of the ON-current and thus the increase in the circuit speed becomes difficult.
In contrast, if the notch-type gate electrode 103 shown in FIG. 1A is employed, the impurity that is obliquely ion-implanted (I.I) through the notch portion 103a of the gate electrode 103 can be injected deeply, as shown in FIG. 4A, like the region in which the gate electrode 103 is not present. Also, when the ions that are obliquely implanted into the gate electrode 103 serving as the visor on the notch portion 103a are passed through the gate electrode 103, a part of such ions loses the energy and reaches the notch portion 103a, so that the ions does not come up to the silicon substrate 101. As a result, as shown in FIG. 4B, the p-type pocket regions 101a do not appear at the shallow portion in the silicon substrate 101 under the notch-type gate electrode 103.
The profile of the pocket regions when the p-type impurity is ion-implanted into the silicon substrate 101, on which the notch-type gate electrode 103 is formed, in the oblique direction from the normal is shown in FIG. 5. In FIG. 5, as illustrated in the area encircled by a broken line, the regions which have the relatively high concentration of the p-type impurity are not present in the channel region of the silicon substrate 101. In this case, the black portions in FIG. 5 denote the portion whose p-type impurity concentration is higher than the channel region.
As a result, if the pocket regions are formed with using the notch-type gate electrode, the ON-current of the transistor can be increased and also the enhancement of the circuit speed can be facilitated, in contrast to the case where the pocket regions are formed by using the gate electrode without the notch. In other words, the desired transistor characteristics cannot be obtained by using the normal gate structure having no notch.
In the prior art, the notch-type gate electrode is formed via following steps by using the method of switching the etching conditions.
First, as shown in FIG. 6A, the polysilicon film 103p is formed on the silicon substrate 101, and then the photoresist 112 having the gate shape is formed thereon.
Then, as shown in FIG. 6B, as the first etching step, the upper portion of the polysilicon film 103p is etched by using the HBr/O2-containing gas while using the photoresist 112 as a mask, so that the upper portion of the polysilicon film 103p left under the photoresist 112 is used as the upper portion of the gate electrode 113. In the first etching step, the etching conditions that make it possible to adhere a plenty of deposition 113a onto the side surfaces of the upper portions of the gate electrode 113 should be set.
Then, as shown in FIG. 6C, as the second etching step, the residual of the polysilicon film 103p is etched by using the photoresist 112 as a mask to form the lower portion of the gate electrode 113. In the second etching step, the etching conditions that make it possible to reduce an amount of the deposition 113b, which is adhere onto the side surfaces of the lower portions of the gate electrode 113, should be set.
Then, as shown in FIG. 6D, as the third etching step, the gate electrode 103 under the photoresist 112 is isotropically etched. In this third etching step, the upper portions of the gate electrode 103 are not narrowed since the side surfaces are protected by the thick deposition 113a, but the lower portions of the gate electrode 103 are narrowed by the isotropic etching since the desposition 113b on the lower portions is thin. As a result, the notches are formed on the side surfaces of the lower portions of the gate electrode 103.
In this case, the notch-type gate electrode 103 is set forth in S. Piddin et al., Symp. VLSI Tec. 2001 p. 35–p. 36, T. Ghani et al., IEDM1999 S17-1, etc.
In addition, the method of forming the pockets at end portions of the source/drain impurity diffusion regions without the above notch-type gate electrode is set forth in Patent Application Publication (KOKAI) Hei 10-294453, for example.
In the pocket forming method in Patent Application Publication (KOKAI) Hei 10-294453, as shown in FIG. 7A, the polysilicon film 115 is formed on the silicon substrate 101 via the gate insulating film 102, then the polysilicon film 115 is unisotropically etched by using the photoresist 112 having the gate shape as a mask, and then the remaining polysilicon film 115 is employed as the gate electrode 115g. Then, as shown in FIG. 7B, the gate electrode 115g on which the photoresist 112 is formed is etched by the wet process in the lateral direction, and thus the gate electrode 115g is narrowed rather than the pattern width of the photoresist 112. Then, as shown in FIG. 7C, the titanium film 116 is formed on the photoresist 112, and thus the visor of the gate electrode 115g is formed by the photoresist 112 and the titanium film 116. Then, in order to form the pocket portions, the p-type impurity is ion-implanted (I.I) in the oblique direction to the substrate surface.
In Patent Application Publication (KOKAI) Hei 10-294453, the steps of forming the silicon nitride film on the silicon substrate, forming the holes each having the inverse trapezoid shape in the silicon nitride film, and filling the gate electrodes made of polysilicon into the holes, whereby the gate electrodes each having the inverse trapezoid sectional shape are formed are set forth. The gate electrodes each having the inverse trapezoid sectional shape are employed as a mask for the pocket formation.
Also, in Patent Application Publication (KOKAI) 2001-267562, it is set forth that a surface of the gate electrode is covered with the contamination-preventing insulating film, then the amorphous silicon film is formed on the contamination-preventing insulating film and the silicon substrate, then the silicon nitride film is formed on the amorphous silicon film, then the silicon nitride film is left on the sides of the gate electrode by applying the unisotropic etching, and then the amorphous silicon film is etched by using the silicon nitride film as a mask.
By the way, as shown in FIGS. 6A to 6D, the notch portions 103a of the gate electrode 103 are formed by selectively isotropically etching the lower portion of the gate electrode 103. However, the state density of the plasma, etc. in the etching chamber is not uniform in etching, and also the etching state becomes uneven on the silicon substrate 101 because of the presence of the density difference of the patterns. Therefore, there is caused the problem that variations in depth and height of the notch portions 103a caused on the substrate surface are increased.
In addition, as shown in FIGS. 7A to 7C, the width of the gate electrode 115g is narrowed rather than the width of the resist mask 112 formed thereon by the isotropic-etching in the wet process. However, if the width of the gate electrode 115g is reduced smaller than 50 nm, for example, it becomes difficult to control the width of the gate electrode 115g by the wet process, so that the variation in the width of plural gate electrodes 115g on the substrate is caused.
Besides, as set forth in Patent Application Publication (KOKAI) Hei 10-294453, it is difficult to form the gate electrodes each having the inverse trapezoid sectional shape in plural in the holes, that are formed in the silicon nitride film to have the inverse trapezoid shape, to have a uniform width. Thus, this is also ready to cause the variation in the width of the gate electrodes.
Moreover, in Patent Application Publication (KOKAI) 2001-267562, since the gate electrode is covered with the contamination-preventing insulating film, a variation in the width of the gate electrode is seldom caused when the amorphous silicon film formed on the gate electrode and the silicon substrate is etched. However, since three types of films having different film quality are formed around the gate electrode and also three types of films must be etched separately, the number of steps is increased. In addition, since the width of the gate electrode is widened substantially by adding the amorphous silicon film, a distance between the gate electrodes cannot be reduced.
As described above, it turns out that it is difficult to control by the conventional structure the width of gate electrode used as a mask of the ion-implantation at the time of forming a pocket part.